2MB Flash, 512KB SRAM, and the external SDRAM 
   Line Driver can collocate with HPLC products 
   PHY layer adopts DSP to increase frequency, MAC layer adopts SoC architecture to easily maintenance. 
   Support up to 256/512/1024/2048 FFT points/ IFFT accelerator 
   Support AES-128192/256 
   Analog module
-  12-bit ADC which possessed 25MSPS
-  12-bit DAC which possessed 25MSPS 
-  Package: LQFP128/ QFN86
   Improve successful rate of data receive: 
-  Design and improve Notch filter to enhance location accuracy
-  Remove 2 interference frequency 
-  Optimize Preamble detection to adopt the exclusive detection to reach the purpose of Robust detection. 
   Greatly improve the calculation of signal physical layer